library ieee;
use ieee.std_logic_1164.all;
use work.control_unit_pkg.all;

entity data_mem_control is
    port (
        OPCODE_i      : in  std_logic_vector(3 downto 0);
        CLK_i         : in  std_logic;
        DATA_MEM_RW_o : out std_logic;
        DATA_MEM_E_o  : out std_logic
    );
end data_mem_control;

architecture behavioral of data_mem_control is
--    constant SV_OPCODE : std_logic_vector(3 downto 0) := "1100";
--    constant LV_OPCODE : std_logic_vector(3 downto 0) := "1101";

    signal is_sv : std_logic;
    signal is_lv : std_logic;

    signal rw_reg : std_logic;
    signal rw_wire : std_logic;

begin

    is_sv <= '1' when OPCODE_i = SV_OPCODE else
             '0';

    is_lv <= '1' when OPCODE_i = LV_OPCODE else
             '0';

    rw_wire <= '1' when is_sv = '1' else
               '0';

    process(CLK_i)
    begin
        if(CLK_i = '1' and CLK_i'event) then
            rw_reg <= rw_wire;
        end if;
    end process;

    -- Write data memory when rw is set
    -- Read data memory when rw is unset
    --DATA_MEM_RW_o <= '1' when is_sv = '1' else
    --                 '0';

    DATA_MEM_RW_o <= rw_reg;

    -- Enable the data memory when is executing a memory instruction
    DATA_MEM_E_o <= '1' when ((is_sv = '1') or (is_lv = '1')) else
                    '0';

end behavioral;

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